TY - JOUR
T1 - An efficient technique to select logic nodes for single event transient pulse-width reduction
AU - Mahatme, Nihaar N.
AU - Chatterjee, Indranil
AU - Patki, Akash
AU - Limbrick, Daniel B
AU - Bhuva, Bharat L.
AU - Schrimpf, Ronald D.
AU - Robinson, William
PY - 2013/1/1
Y1 - 2013/1/1
N2 - An efficient method has been developed to identify logic nodes most likely to generate single-event transients due to p-hits or n-hits. This is weighed against the logical masking effect of gates. Selected gates are hardened by increasing widths of only the restoring devices to reduce single-event error rate. © 2012 Elsevier Ltd. All rights reserved.
AB - An efficient method has been developed to identify logic nodes most likely to generate single-event transients due to p-hits or n-hits. This is weighed against the logical masking effect of gates. Selected gates are hardened by increasing widths of only the restoring devices to reduce single-event error rate. © 2012 Elsevier Ltd. All rights reserved.
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U2 - 10.1016/j.microrel.2012.07.030
DO - 10.1016/j.microrel.2012.07.030
M3 - Article
SN - 0026-2714
VL - 53
SP - 114
EP - 117
JO - Microelectronics Reliability
JF - Microelectronics Reliability
IS - 1
ER -