An efficient technique to select logic nodes for single event transient pulse-width reduction

Nihaar N. Mahatme; Indranil Chatterjee; Akash Patki; Daniel B Limbrick; Bharat L. Bhuva; Ronald D. Schrimpf; William Robinson

doi:10.1016/j.microrel.2012.07.030

An efficient technique to select logic nodes for single event transient pulse-width reduction

Nihaar N. Mahatme
, Indranil Chatterjee
, Akash Patki
, Daniel B Limbrick
, Bharat L. Bhuva
, Ronald D. Schrimpf
, William Robinson

Electrical and Computer Engineering

Vanderbilt University School of Engineering

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

An efficient method has been developed to identify logic nodes most likely to generate single-event transients due to p-hits or n-hits. This is weighed against the logical masking effect of gates. Selected gates are hardened by increasing widths of only the restoring devices to reduce single-event error rate. © 2012 Elsevier Ltd. All rights reserved.

Original language	English
Pages (from-to)	114-117
Number of pages	4
Journal	Microelectronics Reliability
Volume	53
Issue number	1
DOIs	https://doi.org/10.1016/j.microrel.2012.07.030
State	Published - Jan 1 2013

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AU - Schrimpf, Ronald D.

AU - Robinson, William

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An efficient technique to select logic nodes for single event transient pulse-width reduction

Abstract

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