Complementary logic with 60nm poly gate JFET for 0.5V operation

A. K. Kapoor; W. Zhang; S. Sonkusale; Y. Liu; P. Gregory; U. C. Sridharan; C. Stager; N. Eib; Zhijian Xie; M. Vora; J. Prasad; D. Thummalapally; R. Chou

doi:10.1049/el.2010.0742

Complementary logic with 60nm poly gate JFET for 0.5V operation

A. K. Kapoor
, W. Zhang
, S. Sonkusale
, Y. Liu
, P. Gregory
, U. C. Sridharan
, C. Stager
, N. Eib
, Zhijian Xie
, M. Vora
, J. Prasad
, D. Thummalapally
, R. Chou

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n-and p-channel JFET transistors built on bulk silicon and SOI with 60nm gate length operating at 0.5V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16nm. © 2010 The Institution of Engineering and Technology.

Original language	English
Pages (from-to)	783-784
Number of pages	2
Journal	Electronics Letters
Volume	46
Issue number	11
DOIs	https://doi.org/10.1049/el.2010.0742
State	Published - May 27 2010

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10.1049/el.2010.0742

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@article{832bc1bd33a24ccd9ee07b3803fce5dd,

title = "Complementary logic with 60nm poly gate JFET for 0.5V operation",

abstract = "Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n-and p-channel JFET transistors built on bulk silicon and SOI with 60nm gate length operating at 0.5V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16nm. {\textcopyright} 2010 The Institution of Engineering and Technology.",

author = "Kapoor, \{A. K.\} and W. Zhang and S. Sonkusale and Y. Liu and P. Gregory and Sridharan, \{U. C.\} and C. Stager and N. Eib and Zhijian Xie and M. Vora and J. Prasad and D. Thummalapally and R. Chou",

year = "2010",

month = may,

day = "27",

doi = "10.1049/el.2010.0742",

language = "English",

volume = "46",

pages = "783--784",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley and Sons Inc",

number = "11",

}

TY - JOUR

T1 - Complementary logic with 60nm poly gate JFET for 0.5V operation

AU - Kapoor, A. K.

AU - Zhang, W.

AU - Sonkusale, S.

AU - Liu, Y.

AU - Gregory, P.

AU - Sridharan, U. C.

AU - Stager, C.

AU - Eib, N.

AU - Xie, Zhijian

AU - Vora, M.

AU - Prasad, J.

AU - Thummalapally, D.

AU - Chou, R.

PY - 2010/5/27

Y1 - 2010/5/27

N2 - Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n-and p-channel JFET transistors built on bulk silicon and SOI with 60nm gate length operating at 0.5V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16nm. © 2010 The Institution of Engineering and Technology.

AB - Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n-and p-channel JFET transistors built on bulk silicon and SOI with 60nm gate length operating at 0.5V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16nm. © 2010 The Institution of Engineering and Technology.

UR - https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=77952982416&origin=inward

UR - https://www.scopus.com/inward/citedby.uri?partnerID=HzOxMe3b&scp=77952982416&origin=inward

U2 - 10.1049/el.2010.0742

DO - 10.1049/el.2010.0742

M3 - Article

SN - 0013-5194

VL - 46

SP - 783

EP - 784

JO - Electronics Letters

JF - Electronics Letters

IS - 11

ER -

Complementary logic with 60nm poly gate JFET for 0.5V operation

Abstract

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