Complementary logic with 60nm poly gate JFET for 0.5V operation
- A. K. Kapoor
- , W. Zhang
- , S. Sonkusale
- , Y. Liu
- , P. Gregory
- , U. C. Sridharan
- , C. Stager
- , N. Eib
- , Zhijian Xie
- , M. Vora
- , J. Prasad
- , D. Thummalapally
- , R. Chou
- SuVolta, Inc.
- Industrial and systems engineering with North Carolina A&T State University
- Former Consultants at SuVolta, Inc.
Research output: Contribution to journal › Article › peer-review
8
Scopus
citations