Efficient set-bit driven shift-add binary multiplier

Alvernon Walker; Evelyn Sowells-Boone

doi:10.1007/978-3-030-01177-2_99

Efficient set-bit driven shift-add binary multiplier

Alvernon Walker
, Evelyn Sowells-Boone

Computer Systems Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number of bits that are set in one of the input operands except when it equals zero in that case it is one. The multiplier architecture and control logic are presented in this paper. Circuit simulation results are also reported.

Original language	English
Title of host publication	Unknown book
Publisher	Springer Verlag
DOIs	https://doi.org/10.1007/978-3-030-01177-2_99
State	Published - 2019

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10.1007/978-3-030-01177-2_99

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@inproceedings{f0286a13ede947e28c6dd00b7105a8cb,

title = "Efficient set-bit driven shift-add binary multiplier",

abstract = "A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number of bits that are set in one of the input operands except when it equals zero in that case it is one. The multiplier architecture and control logic are presented in this paper. Circuit simulation results are also reported.",

author = "Alvernon Walker and Evelyn Sowells-Boone",

year = "2019",

doi = "10.1007/978-3-030-01177-2\_99",

language = "English",

booktitle = "Unknown book",

publisher = "Springer Verlag",

}

TY - GEN

T1 - Efficient set-bit driven shift-add binary multiplier

AU - Walker, Alvernon

AU - Sowells-Boone, Evelyn

PY - 2019

Y1 - 2019

N2 - A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number of bits that are set in one of the input operands except when it equals zero in that case it is one. The multiplier architecture and control logic are presented in this paper. Circuit simulation results are also reported.

AB - A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number of bits that are set in one of the input operands except when it equals zero in that case it is one. The multiplier architecture and control logic are presented in this paper. Circuit simulation results are also reported.

UR - https://dx.doi.org/10.1007/978-3-030-01177-2_99

U2 - 10.1007/978-3-030-01177-2_99

DO - 10.1007/978-3-030-01177-2_99

M3 - Conference contribution

BT - Unknown book

PB - Springer Verlag

ER -

Efficient set-bit driven shift-add binary multiplier

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