Gate-Level Modeling and Simulation of Single Event Transient Filters

Phillip Gibson; Joshua Govan; Daniel B. Limbrick

doi:10.1109/mwscas53549.2025.11244433

Gate-Level Modeling and Simulation of Single Event Transient Filters

Phillip Gibson
, Joshua Govan
, Daniel B. Limbrick

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper explores gate-level modeling and simulation of Single Event Transient (SET) filters in digital circuits. It demonstrates the feasibility of evaluating SET filter performance using gate-level simulations with the Skywater 130 nm PDK, providing faster analysis than SPICE while maintaining sufficient timing accuracy.

Original language	English
Title of host publication	68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025
DOIs	https://doi.org/10.1109/mwscas53549.2025.11244433
State	Published - 2025

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10.1109/mwscas53549.2025.11244433

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@inproceedings{c4828c70395a436f94698e327850240c,

title = "Gate-Level Modeling and Simulation of Single Event Transient Filters",

abstract = "This paper explores gate-level modeling and simulation of Single Event Transient (SET) filters in digital circuits. It demonstrates the feasibility of evaluating SET filter performance using gate-level simulations with the Skywater 130 nm PDK, providing faster analysis than SPICE while maintaining sufficient timing accuracy.",

author = "Phillip Gibson and Joshua Govan and Limbrick, \{Daniel B.\}",

year = "2025",

doi = "10.1109/mwscas53549.2025.11244433",

language = "English",

booktitle = "68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025",

}

TY - GEN

T1 - Gate-Level Modeling and Simulation of Single Event Transient Filters

AU - Gibson, Phillip

AU - Govan, Joshua

AU - Limbrick, Daniel B.

PY - 2025

Y1 - 2025

N2 - This paper explores gate-level modeling and simulation of Single Event Transient (SET) filters in digital circuits. It demonstrates the feasibility of evaluating SET filter performance using gate-level simulations with the Skywater 130 nm PDK, providing faster analysis than SPICE while maintaining sufficient timing accuracy.

AB - This paper explores gate-level modeling and simulation of Single Event Transient (SET) filters in digital circuits. It demonstrates the feasibility of evaluating SET filter performance using gate-level simulations with the Skywater 130 nm PDK, providing faster analysis than SPICE while maintaining sufficient timing accuracy.

UR - https://dx.doi.org/10.1109/MWSCAS53549.2025.11244433

U2 - 10.1109/mwscas53549.2025.11244433

DO - 10.1109/mwscas53549.2025.11244433

M3 - Conference contribution

BT - 68th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2025

ER -

Gate-Level Modeling and Simulation of Single Event Transient Filters

Abstract

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