Impact of synthesis constraints on error propagation probability of digital circuits

Daniel B. Limbrick; Suge Yue; William H. Robinson; Bharat L. Bhuva

doi:10.1109/dft.2011.46

Impact of synthesis constraints on error propagation probability of digital circuits

Daniel B. Limbrick
, Suge Yue
, William H. Robinson
, Bharat L. Bhuva

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability. © 2011 IEEE.

Original language	English
Title of host publication	2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
DOIs	https://doi.org/10.1109/dft.2011.46
State	Published - 2011

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10.1109/dft.2011.46

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@inproceedings{812e1c3329944e508607535f248cb367,

title = "Impact of synthesis constraints on error propagation probability of digital circuits",

abstract = "Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability. {\textcopyright} 2011 IEEE.",

author = "Limbrick, \{Daniel B.\} and Suge Yue and Robinson, \{William H.\} and Bhuva, \{Bharat L.\}",

year = "2011",

doi = "10.1109/dft.2011.46",

language = "English",

booktitle = "2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011",

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AU - Limbrick, Daniel B.

AU - Yue, Suge

AU - Robinson, William H.

AU - Bhuva, Bharat L.

PY - 2011

Y1 - 2011

N2 - Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability. © 2011 IEEE.

AB - Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit's topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability. © 2011 IEEE.

UR - https://dx.doi.org/10.1109/DFT.2011.46

U2 - 10.1109/dft.2011.46

DO - 10.1109/dft.2011.46

M3 - Conference contribution

BT - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011

ER -

Impact of synthesis constraints on error propagation probability of digital circuits

Abstract

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